Encoding Multiple Pixel - Dynamic TDATA Configuration - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

For applications where video IP can dynamically change color-component width, video format, or the number of pixels/samples per data beat, pixels and components should remain at the static locations determined by the generic parameters for instantiation. For example, if only one pixel is transmitted over an interface supporting at most two pixels per data beat, the sample/pixel should be aligned to the least significant pixel position. Similarly, if only 8 bits per component are transmitted over an interface generated for 10 bits per component, the active bits should be MSB aligned and LSB padded with zeros. Three examples are shown in This Figure through This Figure .

IMPORTANT: Although this specification supports dynamically changing the number of pixels/samples per data beat, this is not recommended because not all IPs support this feature.

Figure 1-6: One Pixel per Data Beat, Eight Bits per Component over a Two-Pixel per Data Beat, 10-Bits per Component Bus

X-Ref Target - Figure 1-6

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Figure 1-7: Two Pixels per Data Beat, Eight Bits per Component over a Two-Pixel per Data Beat, 10-Bits per Component Bus

X-Ref Target - Figure 1-7

X22097-1-7.jpg

This Figure . captures RGB888 (pixel with three components, component width of 8).

Figure 1-8: Two Pixels per Data Beat, Eight bits per Component (RGB888, VF Code 2) over a Two-Pixel per Data Beat, 14-bits per Component Bus

X-Ref Target - Figure 1-8

X22098-1-8.jpg

Notes:

1. Each G,B,R component sits in 14-bit component space with MSB alignment.

This Figure . captures RAW14 (pixel with single component, component width of 14).

Figure 1-9: Two Pixels per Data Beat, 14 Bits per Component (RAW14, VF Code 12) over a Two-Pixel per Data Beat, 14-bits per Component Bus

X-Ref Target - Figure 1-9

X22099-1-9.jpg

Notes:

1. Although RAW14 may only use the lower 28 bits, the full AXI4-Stream interface remains 88-bits because it must accommodate the possibility of switching to RGB at full 14-bits per color if requested when dealing with dynamic TDATA. Down stream logic must be aware of this and should provide the appropriate bus interface and then internally discard bits if it does not use them.

Comparing the two data type component widths in This Figure and This Figure , the RAW14, VF Code 2 data type has 14-bit component and RGB888 (VF Code 2) 8-bit component. Therefore, the RGB888 components are placed with MSB aligned and LSB padded with zeros on 14-bit component bus. Additionally, the RAW14 pixels are packed tightly together.