Flushing Pipelined Cores - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

Pipelined IP cores must maintain the consistent validity of data in pipeline stages from beginning to end of video lines. For example, if horizontal FIR filtering is performed to generate valid output samples, all taps of the FIR filter delay line should only contain valid pixels. If valid data is not always present on the input (slave) interface of the filtering core, the clock-enable pins of the delay-line and the filter arithmetic should be pulsed to latch in and process only valid input samples. This implies that data in the processing pipeline of the IP core only moves forward when new, valid samples are available to process. Take for example a Color-Space Converter processing streaming video with horizontal and vertical blanking periods where no valid samples are transferred over the AXI4-Stream video interfaces for a large number of ACLK cycles. This behavior would imply that the results corresponding to the end of scan line are only available when the samples from the beginning of the next line clock them out. Similarly, the last samples from the end of a frame only become available at the beginning of the next frame. Both behaviors are prohibited because they introduce processing bubbles that break the output interface data-sync alignment.

Instead, processing pipelines must be flushed at the end of each scan-line. If samples for the next line (and next frame) are available immediately, processing cores can use these samples. If samples are not available, processing cores can flush pipelines by repeating the last valid pixel or applying a more sophisticated edge padding solution. If padding by zeros or repeated samples from the next line are needed in preparation for the next line or next frame, a processing core might deassert its READY input for as many clock cycles as it takes to empty valid data samples from the pipeline or to pad and re-initialize for a new line.

Figure 3-5: Simple Video IP with One Slave and One Master AXI4-Stream Interfaces

X-Ref Target - Figure 3-5

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When flushing is completed and the pipeline is empty, processing cores should assert the READY output signals on the slave interfaces irrespective of the READY inputs of the master interfaces, as seen in the READY_out and READY_in signals of This Figure and described in READY – VALID Propagation .

Figure 3-6: Inefficient Flushing Growing a Processing Bubble at the End of Frame

X-Ref Target - Figure 3-6

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If the READY output signal ( READY_out ) assertion is delayed until the slave interface READY_in is asserted, subsequent cores would keep inserting longer breaks between lines/frames, as illustrated on This Figure . In this example, the gap between frames/lines of the input stream grows because the flushing periods of subsequent cores accumulate if the IP core holds off re-asserting its READY_out output until its READY_in is asserted.