Bits 0 to 3 ( VIDEO_FORMAT ) define the sampling structure of video using the video format codes (VF) defined in Table: Video Format Codes and Data Representation for C_tk_MAX_SAMPLES_PER_CLOCK =1 . Bits 4-5 define the data representation, the number of bits per component channel, as defined in Table: Data Representation Codes .
|
ENCODING[5:4] |
Bits per Component Channel |
|---|---|
|
00 |
8 |
|
01 |
10 |
|
10 |
12 |
|
11 |
16 |
Bit 6 ( INTERLACED ) should be set if the video processed is interlaced (1). For progressive video, this bit should be set to 0. Corresponding Bit 7, indicates field polarity (0: even field, 1: odd field) if interlaced video is used. Processing cores should not expect the host processor to update this register value on a frame-by-frame basis. Instead, the IP is expected to toggle automatically after processing fields, using the programmed value as the initial value for the first field after the value is committed.
Bit 8 ( CHROMA_PARITY ) of the ENCODING register specifies whether the first line of video contains chroma information (1) or not (0) when YUV 420 encoded video is being processed. Processing cores should not expect the host processor to update this register value on a line-by-line basis to reflect whether the current line contains chroma or not. Instead, the IP is expected to toggle automatically after each line was processed, using the programmed value as the initial value for the first line of the first frame after the value is committed. Table: Typical Values for Timing Variables provides example values for timing variable assignments for typical video standards using 8 bit data.