General IP Structure - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

Video IP cores should provide an AXI4-Lite interface option to allows dynamic read and write processing parameters, status and control data, and timing parameters. For embedded systems using either a processor or dedicated IP acting as the AXI4-Lite master, an AXI4-Lite interface should be provided with a standardized register API. For systems without an embedded processor, video cores should provide a way to be instantiated, supporting one fixed video resolution.

This Figure is a schematic for a typical video processing core with one AXI4-Stream slave input, one AXI4-Stream master output, and an AXI4-Lite interface. In this example, the IP core processing the input and the output AXI4-Stream interfaces are apart of the same clock domain ( ACLK ), but the AXI4-Lite processor interface input is in the AXI4-Lite processor clock domain. Typically the AXI4-Lite interface does not use the same clock as the AXI4-Stream video slave and master interfaces. Therefore, the IP should contain Clock-Domain Crossing (CDC) logic to facilitate re-sampling the AXI4-Lite register data to the processing core clock domain.

Figure 3-1: General Video IP Structure with AXI4-Lite and AXI4-Stream Interfaces

X-Ref Target - Figure 3-1

X22110-3-1.jpg

All video IP cores should contain control logic to govern the propagation of VALID and READY signals, enable/disable/initialize the core Signal Processing Function, manage internal buffers, generate SOF and EOL signals, and monitor error conditions. See READY – VALID Propagation and Flushing Pipelined Cores for more information.