The handshaking mechanism of AXI4-Stream provides a framework that allows building video systems that align data and timing signals without having to manually calculate propagation delay through processing blocks, as well as creating frame sync signals to trigger certain blocks. For data and output sync signal alignment, consider the following design constraints:
• Is it possible to hold up the input video stream? Is there a back pressure signal?
• Must the output stream be phase-locked to an external Frame Sync signal?
• Are the input and output video clocks the same or phase-locked to each other?
Based on the above consideration, typical use cases include:
• Timed video input, such as DVI, that cannot be delayed. Timed video output using the same video clock. For automatic delay matching, synchronization is necessary.
• Input and output are in unrelated clock domains (scaled video), and a frame buffer is necessary.
No delay matching is necessary in a hardware accelerator scenario where input is coming from memory or from a processor. Processing and output blocks can generate output when the input is available. If input and output are in unrelated clock domains, a frame buffer is necessary. The following sections contain recommendations for implementing protocol-based delay matching for scenarios with or without frame buffers.
In all cases, the input interface module is expected to have a “locked” output, originating from the VTC timing detector. The VTC timing detector issues a signal when the input timing measurements are stabilized. The input interface module is expected to drop pixel data until input timing has locked.