The recommended design convention for AXI4-Stream component interfaces suggests that outputs should be registered or driven directly by flip-flops or FIFO/block RAM primitives. Ideally, inputs are also registered but can be combinatorial. Combinatorial inputs can limit Fmax so the amount of combinatorial logic present on inputs should be limited.
There must be no combinatorial paths between input and output signals on either master or slave interfaces. Combinatorial paths between input and output signals are not permitted across separate AXI4-Stream interfaces. In some cases, outputs driven by combinatorial logic are a suitable design choice or a reasonable design trade-off, such as when latency is critical. The IP core data sheet describes AXI4-Stream output signals that are not registered.