Interrupt Subsystem - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

Video processing cores should provide optional interrupt pin ( IRQ ). Timing and core function related STATUS and ERROR flags, described in Table: Standard Video IP Registers , should be individually selectable to generate an interrupt.

In EDK, the interrupt controller ( INTC ) IP can be used to integrate IRQ pins for the system processor. For Vivado® tools, you might need to create a custom built priority interrupt controller to aggregate interrupt requests and identify interrupt sources.

Video IP core APIs, including registers and driver functions, should enable application software developers to identify and clear interrupt sources within the IP.