All cores that cannot process pixels fast enough to sustain one pixel per output clock need output line-buffer(s) to avoid stalling the pipeline. Although combining line buffers at the end of a processing pipeline (by taking advantage of an output interface core with programmable line-buffer depth) might seem like an attractive option to save resources, it can also defeat the purpose of buffering.
In this example, ( This Figure ) a hypothetical output interface needs to generate frames with 320 clock cycles per line, with 200 active pixels per line. The external memory interface retrieves pixels in 64 pixel bursts after which it is unavailable for 16 clock cycles. Core A takes 3 clock cycles to generate 2 output pixels. Core B takes three line periods to generate two active lines (no output for the 960 pixels, then 400 pixels consecutively).
Although all cores (external memory, Core A, Core B) have the throughput necessary to generate 200 pixels per 320 clock cycles on the average, the throughput degrades unless there are line buffers on each core output when connected as a system. For example, if the external memory provides data in 64 cycle bursts, Core A produces 42 output samples per burst or 170 pixels per line. Core A requires the whole line period to produce the active pixels, but it is forced to idle during the 4x16 cycles when the external memory is not available.
To avoid processing bubbles, all cores should be appropriately buffered on the output of the core as if the core was driving the output interface directly. This Figure illustrates the scenario when processing cores can maintain the line-pixel rate, but cores need output buffers to avoid processing bubbles. Green arrows represent subsequent cores reading from the output buffers of preceding cores.