Multipoint Interfaces - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

Some applications require a single AXI4-Stream master interface connected to multiple slaves, such as a stream splitter, or multiple master interfaces to be connected to a single slave, such as a stream combiner.

For video applications, the use of stream combiners is discouraged. Without the TID and TDEST fields, pixel sources are ambiguous. The recommended solution is to create separate slave component interfaces on the receiver IP to the IP to distinguish data received from different sources, if necessary. No explicit video IP is provided to split AXI4-Streams. HDL and EDK users can easily implement the video splitter with AND gates.

Example: 1-to-2 splitter implemented in VHDL

source_READY   <= target1_READY and target2_READY;

target1_VALID  <= source_VALID  and target2_READY;

target2_VALID  <= source_VALID  and target1_READY;

The example above assumes downstream target interfaces asserting READY as soon as the target is ready to receive data, independent from VALID . Otherwise, a small, distributed memory based FIFO must be inserted between the splitter and the target to avoid deadlocks.