This section provides an algorithm for automatic data–sync signal alignment at the output interface for a video system that contains a frame buffer, and the output video stream might be in a separate clock domain or might have to be phase-locked to an external Frame Sync signal ( This Figure ).
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X-Ref Target - Figure 2-3 
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The portion of this system relevant to output stream synchronization is the leg from the frame buffer to the output interface core, which can contain processing cores. These processing cores can change the effective pixel rate. The example presented in This Figure uses a video scaler, which typically changes the pixel rate, and can operate in three different clock domains:
• its input interface running at the memory system clock rate
• the core processing data at a processing clock rate
• its output interface running at the same clock as the output interface, which can come from an external clock source
The choice of external frame buffer for AXI4-Stream based IP video systems is the AXI-VDMA core, which must be configured to the desired frame size using an AXI4-Lite interface. This Figure illustrates timing information (from an input interface core, or from software) distributed using this interface.
Three possible scenarios are addressed in this setup:
1. External output clock ( Ext clk ) is different from the input clock, but there is no external Fsync signal.
2. Output Timing Generator needs to be locked to an external Fsync .
3. External Fsync driving the AXI-VDMA readouts.
For scenario 1, the data – sync signal alignment algorithm is as follows:
After power up or reset, the output interface core should deassert READY and set all outputs to defaults until timing information is locked ( This Figure ). The AXI-VDMA should be configured with the write side being Fsync and Genlock master. When the input buffer of the Video output core is 50% filled with data from the AXI-VDMA, the output timing signal generation should commence. When the timing generator gets to the phase where active video needs to be sent, but pixels are not present yet, blank frames should be generated. If the output interface data buffer gets full, the output interface core should deassert TREADY .
For scenario two, the setup and protocol are identical, but the video timing generator should be configured to sync with the external Fsync .
For scenario 3, a frame sync signal originating from the output timing generator or an external fsync is used to trigger AXI-VDMA frame reads. If an external frame sync signal is present, ensure that the phase relationship between the external Fsync pulse and the VTC generator Fsync allows pixel data to be fetched from the AXI-VDMA and propagated through subsequent cores between the AXI-VDMA and the output interface module. This allows data and timing signals on the output interface to be synchronized.
A good example of this is when the external frame sync is in phase with the start of vertical blanking. If output pixels are needed immediately, this sync is too late to trigger readout from the AXI-VDMA.
The timing generator core contains logic which can generate frame sync pulses at arbitrary phases after the generator is generating periodic timing signals. For scenarios when the external frame sync is too late to trigger data readout, an earlier, regenerated frame sync pulse should be used. This ensures that pixel data gets to the output interface core before it needs to be sent in phase with the periodic output timing signals.
For video systems with a Frame Buffer but no external output frame sync source, the AXI-VDMA core can automatically fetch the last frame finished on the write-side to be picked up immediately when the read size is in idle (reading a frame has completed).
When pixel data propagates to the output interface core, the output interface core should deassert its READY output and start driving pixel data using READY to maintain synchrony between the input pixel flow and output sync signals.