This section provides an algorithm ( This Figure ) describing how automatic data-sync signal alignment can be achieved at the output interface for a video system that contains
• no frame buffer
• a periodic input stream that cannot be held off
• an output video pixel clock that is either the same, or a derivative of the input pixel clock, and
• the output video stream does not have to be phase locked to an external Frame Sync signal.
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X-Ref Target - Figure 2-2 
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This scenario applies to a sensor image pre-processing pipeline, where input and output pixel rates are identical, and the output timing generator does not have to be locked to an external frame sync source. After power on or reset, the output AXI4-Stream interface deasserts READY , and the output timing signal generator state machine is initialized to wait in the state just before the start of active video.
Note: In this case, the function of READY is limited to what the internal buffers allow if the input stream cannot be held back.
The output timing generator waits for the input interface to signal that timing information has stabilized (locked). Now, the output AXI4-Stream interface should assert READY , which propagates backward towards the input of the pipeline. As a result, pixel data is propagated down the pipeline. Processed pixel data reaches the output interface module when its VALID input is sampled high. When the input data buffer of the output video interface gets 50% full, the output timing generator can start generating periodic output sync/blank signals, and pixel data can be fed forward to the output.