Input and Output interface IP should provide two interface options to make measured timing information available for subsequent cores. For embedded systems either using a processor or dedicated IP acting as the AXI4-Lite master, an AXI4-Lite interface should be provided with a standardized register API to present timing information. For standalone video systems without an embedded processor, timing parameters for a fixed format/resolution should be provided through the IP parameters and/or GUI. The Video Timing Controller (VTC) core contains the Timing Detector and Timing Generator cores for use with custom AXI4-Stream interfaces.
The Video to AXI4-Stream and AXI4-Stream to Video cores are delivered as HDL source code and provided as examples to expedite custom interface development. For embedded systems using a processor acting as an AXI4-Lite master or dedicated IP acting as the AXI4-Lite master, an AXI4-Lite pCore interface should be provided with a standardized register API to present timing information. For more information, see AXI4-Lite Interface .
Using the TUSER signal to transmit periodic sync information, such as hsync or vsync along with the video data is prohibited as there are no guarantees on IP delay consistency (aperiodicity), and delay matching between DATA and TUSER bits through IP cores. Furthermore, when video data is written and retrieved from frame buffers, sync information from TUSER is not recovered.
Transferring timing information or ancillary data embedded in the AXI4-Stream video stream is also prohibited, either in the form of a header or as a watermark. No method is provided for, or expected from processing cores to distinguish timing information or ancillary data packets from valid pixel data. When video data is re-formatted, for example video scaling changes the active frame dimensions, no mechanism is provided or expected to change timing or stream information embedded in video data.