READY – VALID Propagation - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

For very simple IP cores, propagating VALID from master to slave and propagating READY from slave to master seems straight-forward. However, when the IP core has pipeline registers and/or FIFOs, the internal state of pipelines and FIFOs must be factored in to the READY / VALID output assignments. See Buffer Management for more information.

As stated in Input/Output Timing , the READY output on the slave interface and VALID output on the master interface must be registered. This requirement inserts a propagation delay of at least one clock cycle between the deasserted READY signal on the IP core slave interface input and the master interface READY output. The logic controlling these outputs, as well as the latching in of new pixels from the slave interface to internal FIFOs or pipeline registers, must consider the scenario when all internal buffers (pipeline registers and FIFOs) are full, the downstream slave interface just deasserted READY , but the upstream master interface sends one more pixel due to the core master interface READY signal lagging behind the slave interface.

To avoid pixel drops in the above situation, pipelined cores without internal FIFOs should contain one (or more) additional pipeline stage(s) to accept one (or more) pixel(s). These cores should keep the master interface READY output deasserted until the extra pipeline stage is processed.

To mitigate the pixel drop condition for cores with internal FIFOs the master interface READY output should be asserted unless:

all pipeline stages are full, internal FIFOs are almost full, and the master interface READY is sampled low.

internal pipelines need to be flushed.