READY/VALID Handshake - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

A valid transfer occurs whenever READY , VALID , ACLKEN , and ARESETn signals are High at the rising edge of ACLK , as shown in This Figure .

Figure 1-2: Example of READY/VALID Handshake, Start of a New Frame

X-Ref Target - Figure 1-2

fig2.PNG

During valid transfers, DATA only carries active video data. Blank periods and ancillary data packets are not transferred by video over AXI4-Stream.