Register Synchronization - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

Most control registers that provide frame-by-frame control over processing should be double-buffered to ensure no image tearing occurs if register values are modified while a frame is being processed. Exceptions are registers which command immediate actuation ( CONTROL , STATUS , ERROR and IRQ_ENABLE registers) or need to be changed multiple times within a frame (a readout or coefficient address register). With double buffering, register writes are updating the first set of registers while the processing core uses values from a second set of registers. All writable registers are also readable. Any reads from writable registers return values that are stored in the first set of registers.

A semaphore mechanism allows you to update multiple registers without having all updates take place within a single frame or between frames.

Values from the first register set should be copied over (committed) to the second register set when processing cores receive the SOF signal and semaphore flag REG_UPDATE , located on bit 1 of register CONTROL , is set.

deasserting REG_UPDATE allows applications to modify multiple registers at any time without causing any artifacts with incomplete intra-frame updates. By asserting REG_UPDATE , congruently updated registers are being used for the subsequent frames starting at the next frame boundary.