When resetting multiple video cores within a system, all interfaces must be reset before any interface comes out of reset. When reset is performed in the software (which asserts/deasserts software reset flags sequentially), the IP cores should be reset from the output towards the input. The software reset pin of video IP closest to the system output should be asserted first. Subsequent cores near the signal source should then be reset. Software reset pins should be deasserted in the same sequence.
If permitted by the application, provide a soft software reset option (SSR) for the video IP, where reset is synchronized with video frame boundaries. If sufficient time is available between video frames, (for example, a vertical blanking period is present), a soft reset after the predicted end-of-frame can facilitate the reset of individual cores without negatively impacting system performance.