Status and Error Registers - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

When using the AXI4-Lite interface, it is recommended that processing events and errors assert STATUS and ERROR register flags. The event flags should remain set until the application clears the flags, or the core is reset. STATUS register flags should be able to trigger interrupts through an IRQ pin. Bits of the STATUS and ERROR registers should be individually toggled when the application writes a '1' to the appropriate bit position of the STATUS and ERROR registers.

If the core does not provide an AXI4-Lite interface, the IP should be configured to provide notification of critical status and error events through a dedicated set of pins. These pins can be connected to an external interrupt controller (INTC) core in an EDK system to facilitate interrupt requests, identification, and clearing of interrupt sources. For this application, it is recommended that the dedicated output signals remain asserted only as long as the status or error event persists.