Streaming Video Input Connection - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

As illustrated in This Figure , the Video In to AXI4-Stream core (VID-IN) is provided to interface periodic video, such as HDMI or DVI to AXI4-Stream, and is intended for use with the Video Timing Controller (VTC). Together, the VTC processes timing signals and the VID-IN core buffers input video data (as necessary) before transmission over AXI4-Stream. The VTC core can process one of the following sets of timing signals:

Vsync, Hsync, and DE

Vblank, Hblank, and DE

Vsync, Hsync, Vbank, Hblank, and DE

The choice of timing signal sets should be specified when generating the VTC core.

This Figure shows a typical example of connecting the VID-IN and VTC cores to downstream video processing cores (“Video IP Sink”) through AXI4-Stream interfaces.

Figure 2-5: Connecting the Video to AXI4-Stream Core to the Video Timing Controller

X-Ref Target - Figure 2-5

vtc_video_in.jpg

At startup, the following points should be considered:

The VID-IN core should not start sending data to downstream core(s) until they are enabled and initialized.

The VID-IN core should not start sending data to downstream cores until the VTC cores is enabled, initialized, and locked.

After the start of streaming video, bootup, or resetting the system, the VTC core can take more than a full frame of data to accurately measure all timing parameters. During this time the locked status bit of the VTC, available through bit 8 of the optional INTC_IF interface, is 0. It is recommended to connect INTC_IF[8] to the axis_enable input of VID-IN core. This hardware configuration ensures that no video is sent before the VTC is locked.

Xilinx recommends that the VTC detector be enabled only after the rest of the downstream processing cores are all initialized and enabled. Otherwise, the output FIFO within the VID-In core can become full while downstream cores initialize in the pipe, ultimately resulting to lost pixels, lines, and/or frames of video.

If the downstream IP core need to know the input resolution before it can be configured, the you should:

1. SW Reset and SW disable all processing cores and the VTC

2. Enable the VTC to detect input resolution.

3. Once the VTC is locked, read measured resolution.

4. Reset the VTC

5. Configure the downstream IP.

6. Enable the downstream IP.

7. Enable the VTC