To debug frame-buffer bandwidth limitation issues, and if possible allow video application software to balance memory pathways, video IP cores should offer frame, line, and pixel counter registers.
The recommended name and location of these registers are SYSDEBUG0 , SYSDEBUG1 and SYSDEBUG2 , as indicated in Table: Standard Video IP Registers . The registers should initialize to 0 after reset, but the core might implement other, additional mechanisms to clear the counters.