Timing information captures the phase/edge relationships between four periodic timing signals:
• Vertical Sync ( VSync )
• Horizontal Sync ( HSync )
• Vertical Blank ( VBlank )
• Horizontal Blank ( HBlank )
Timing detector/timing generator modules provided as part of the Xilinx Video Timing Controller core measure and regenerate timing signals. For an embedded processor with AXI4-Lite interface, measured timing information is accessible through a standardized register set, described in Table: Standardized Timing Registers .