AXI4-Stream carries only video pixel data, SOF , and EOL signals between component interfaces. Blanking or sync signals are not carried by the signaling interface, and strict signal periodicity is not required.
In addition to extracting video pixel data from the input stream and sending it to subsequent modules using video over AXI4-Stream, the interface modules must measure timing information (including the number of pixels per scan-line, number of active rows per frame, and so on) when receiving video from a standard periodic video source such as DVI, HDMI, SDI, or an image sensor. Input interface modules make this information available to video processing and output interface modules, which then recreate periodic timing signals and embed output video pixel data that was processed by the video system to recreate a periodic output stream such as DVI ( This Figure ).
This Figure illustrates the extraction and propagation of timing information. The Video In to AXI4-Stream input interface and Video Timing Detector cores measure timing information, and extract video pixel data. It then transmit the data using the AXI4-Stream (represented by the AXI4-S arrows in This Figure ). Timing information is propagated through optional AXI4-Lite interfaces. When present, the system processor (AXI4-Lite master) reads out measured timing information from the timing detector, and programs subsequent processing cores and the timing generator using the AXI4-Lite control register interfaces. When instantiated without an AXI4-Lite control interface, video cores can only process a fixed video format / resolution, specified in the core GUI. In This Figure , the Chroma Resampler and Enhance cores process the video stream. The processing cores might contain line buffers for which the number of active pixels per scan line is necessary. The processing cores receive active size (number of pixels per scan line, number of scan lines per frame) measurement values, among other timing parameters from the Video Timing Detector module, which is used with the DVI input interface IP. Processing cores also verify the data by employing pixel counters between subsequent EOL pulses. The AXI4-Stream to Video output interface core generates Standard Sync, Blank and Active Video timing signals, as defined by the timing information received, and embeds the video pixel data as received over the AXI4-Stream input interface.