When Timing Information Is Incorrect - 1.0 English

AXI4-Stream Video IP and System Design Guide (UG934)

Document ID
UG934
Release Date
2022-11-16
Version
1.0 English

This situation can arise if any of the AXI-VDMA frame dimensions, the scaler frame dimensions or ratios, or the output interface timing parameters are programmed incorrectly ( This Figure ).

There could be a discrepancy between measured frame dimensions based on EOL and SOF locations and the frame dimensions provided to the VTC generator side and the processing cores through the core GUI or the AXI4-Lite register interface.

If the SOF and EOL framing signals occur early, processing cores should immediately start processing the new line or new frame. If the framing signals are late, processing cores should purge partial frames by dropping pixels until the expected SOF or EOL signal is received.