Xilinx Video IP supports Interlace content using field_id or fid interface as a separate port along with AXI4S-Video interface. The field_id signal indicates the polarity of the field when the video is interlaced. This signal is only used with interlaced data and set to zero for progressive video inputs. The field_id signal changes with the rising edge of Start of Frame/Field (TUSER) of the AXI4-Stream interface. The following IPs help handle the interlaced content effectively using field_id signal.