To create a project, use the New Project wizard to name the project, add RTL source files and constraints, and specify the target device.
- Invoke Vivado IDE.
- In the Quick Start tab, click Create Project to start the New Project wizard. Click Next.
- In the Project Name page, name the new project proj_hdl_vio and provide the project location (C:/Vivado_Debug). Ensure that the Create project subdirectory is selected. Click Next.
- In the Project Type page, specify the Type of Project to create as RTL Project. Click Next.
- In the Add Sources page:
- Set Target Language to VHDL.
- Click Add Files.
- In the Add Source Files dialog box, navigate to the /src/lab3 directory.
- Select all VHD source files, and click OK.
- Verify that the files are added, and Copy Sources into Project is selected.
- Click the “+” sign, and click Add Directories.
- In the Add Source Directories dialog box, navigate to the /src/lab3 directory and choose the sine_high, sine_low, sine_mid, and ila_0 directories. Click Select.
- Verify that the directories are added, and Copy sources into the project are selected. Click Next.
- In the Add Constraints dialog box, click the “+” sign, and click Add Files.
- Navigate to the /src/lab3 directory and select sinegen_demo_kc705.xdc. Click Next.
- In the Default Part page, specify the xc7k325tffg900-2 platform. You can also select Boards and select Kintex 7 KC705 Evaluation Platform. Click Next.
- Review the New Project Summary page. Verify that the data appears as
expected by the previous steps. Click Finish.Note: It might take a moment for the project to initialize.
- In the Sources window in Vivado IDE,
expand sinegen_demo_inst_vio to see the
source files for this lab. Note: The ila_0 core is added to the project. However, vio_0 (the VIO core) is missing.
- Instantiate and configure this VIO core as follows. From the Flow Navigator, click IP Catalog, expand Debug & Verification, expand Debug, and double-click VIO. The Customize IP dialog box opens.
- On the General Options tab, leave the Component Name as its
default value of vio_0, set Input Probe Count to 1, Output Probe Count to 1, and select the Enable Input Probe
Activity Detectors check box.
- On the PROBE_IN Ports tab, set Probe Width to 4.
- On the PROBE_OUT Ports tab, set Probe Width to 2 and Initial Value to 0x0.
- Click OK to generate the IP. The
Generate Output Products dialog box appears. Click Generate. An additional dialog box can appear, indicating an
out-of-context module run is launched. If so, click OK.
Output product generation should take less than a minute. At this point, you have finished customizing the VIO. This core is already instantiated in the top-level design.
At this point, the Sources window should look as shown in the following figure.
- Double-click sinegen_demo_inst.vhd in the Sources window to open it, and inspect the instantiation and port mapping of the ILA core in the HDL code.