Step 2: Program the KC705 Board and Interact with the JTAG to AXI Master Core - 2023.2 English

Vivado Design Suite Tutorial: Programming and Debugging (UG936)
Document ID
UG936
Release Date
2023-11-01
Version
2023.2 English
  1. Connect your KC705 board's USB-JTAG interface to a machine with AMD Vivado™ IDE and cable drivers installed and power up the board.
  2. The Hardware Manager window opens. Click Open New Target. The Open New Hardware Target dialog opens.

  3. In the Connect to field, choose Local server, and click Next.

    Note: Depending on your connection speed, this can take about 10 to 15 seconds.
  4. If more than one target is connected to the hardware server, you see multiple entries on the Select Hardware Target page. In this tutorial, only one target is shown in the following figure. Leave these settings at their default values, and click Next.

  5. Leave these settings at their default values as shown. Click Next.
  6. In the Open Hardware Target Summary page, click Finish, as shown in the following figure.

    Wait for the connection to the hardware to complete. After the hardware target is connected, the Hardware dialog shown in the following figure opens.

    Note: The Hardware tab in the Debug view shows the hardware target and XC7K325T device detected in the JTAG chain.


  7. Next, program the previously created XC7K325T device using the .bit bitstream file by right-clicking the XC7K325T device, and selecting Program Device as shown in the following figure.
  8. In the Program Device dialog, verify that the .bit file is correct for the lab on which you are working. Click Program to program the device.

    Note: Wait for the program device operation to complete. This can take a few minutes.
  9. Verify that the JTAG to AXI Master and ILA cores are detected by locating the hw_axi_1 and hw_ila_1 instances in the Hardware Manager window.

  10. You can communicate with the JTAG to AXI Master core via Tcl commands only. You can issue AXI read and write transactions using the run_hw_axi command. However, before issuing these transactions, it is important to reset the JTAG to the AXI Master core. Because the aresetn input port of the jtag_axi_0 core instance is not connected to anything, you need to use the following Tcl commands to reset the core:
    reset_hw_axi [get_hw_axis hw_axi_1]


  11. The next step is to create a 4-word AXI burst transaction to write to the first four locations of the BRAM: 
    set wt [create_hw_axi_txn write_txn [get_hw_axis hw_axi_1] -type WRITE -address C0000000 -len 128 -data {44444444_33333333_22222222_11111111}]

    where:

    • write_txn is the name of the transaction.
    • [get_hw_axis hw_axi_1] returns the hw_axi_1 object.
    • -address C0000000 is the start address.
    • -len 128 sets the AXI burst length to 128 words
    • -data {44444444_33333333_22222222_11111111} is the data to be written.
    Note: The data direction is MSB to the left (that is, address 3) and LSB to the right (that is, address 0). The data is repeated from the LSB to the MSB to fill the entire burst.
  12. The next step is to set up a 128-word AXI burst transaction to read the contents of the first four locations of the AXI-BRAM core:
    set rt [create_hw_axi_txn read_txn [get_hw_axis hw_axi_1] -type READ -address C0000000 -len 128]

    where:

    • read_txn is the name of the transaction.
    • [get_hw_axis hw_axi_1] returns the hw_axi_1 object.
    • -address C0000000 is the start address.
    • -len 128 sets the AXI burst length to 4 words.
  13. After creating the transaction, you can run it as a write transaction using the run_hw_axi command:
    run_hw_axi $wt

    This command should return the following:

    INFO: [Labtools 27-147] : WRITE DATA is : 44444444333333332222222211111111…
  14. After creating the transaction, you can run it as a read transaction using the run_hw_axi command:
    run_hw_axi $rt

    This command should return the following:

    INFO: [Labtools 27-147] : READ DATA is : 44444444333333332222222211111111…