The Virtual Input/Output (VIO) core is a customizable core that can both monitor and drive internal FPGA signals in real time. The number and width of the input and output ports are customizable in size to interface with the FPGA design. Because the VIO core is synchronous to the design being monitored and/or driven, all design clock constraints that are applied to your design are also applied to the components inside the VIO core. Run time interaction with this core requires the use of the Vivado® tool's logic analyzer feature. The following figure is a block diagram of the new VIO core.
This lab walks you through the steps of instantiating and configuring the VIO core. It walks you through the steps of connecting the I/Os of the design to the VIO core. This way, you can debug your design when you do not have access to the hardware or the hardware is remotely located.
The following ports are created:
- One four-bit PROBE_IN0 port. This has two bits to monitor the two-bit Sine Wave selector outputs from the finite state machine (FSM) and other two bits to mimic the state of the other two LEDs on the board. You will configure these four-bit signals as LEDs during run time to mimic the LEDs displayed on the KC705 board.
- One two-bit PROBE_OUT0 port to drive the input buttons on the FSM. You will configure it so one bit can be used as a toggle switch during run time to mimic PUSH_BUTTON switch SW3, and the second bit will be used as PUSH_BUTTON switch SW6.