Feature Covered - 2022.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2022-05-31
Version
2022.1 English
The following features are covered in the GTM-Wizard:
  1. Detection of designs with PAM4 signals, designs instantiating GTM_DUAL and automatic generation bypass module (xil_dut_bypass).
  2. Simple sanity check for design that should instantiate bypass module.
  3. A mechanism to view PAM4 signals in Waveform Viewer for XSim users.
  4. Provide a way to generate bypass module for export simulation flow.

In this tutorial, we would generate an GTM-Wizard example design, which usage PAM4 signal. To generate that, please follow steps below:

  1. Create project in Vivado 2022.1 without adding source/constraint file Create project > next > next > next > next > next.
  2. In the Default Part page, select Virtex UltraScale+ 58G and select parts as shown in the following figure and click Next.

  3. Check the summary report and click Finish.

  4. Under Project Manager, click on IP Catalog and search for gtm_wizard and then double-click Virtex UltraScale+ FPGAs Transceivers Wizard.