Object Window - 2022.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2022-05-31
Version
2022.1 English
In System Verilog, all the net/variables are static type. They exist throughout the simulation. In System Verilog, dynamic type is a new type along with static type. Class, Queue, and Associative Array are some examples of dynamic type.

Unlike static type variables (int a; wire [7:0] b;), dynamic type variables do not have a fixed size throughout the simulation. Variables keep changing during run-time. Through Object window, you can view the value of a dynamic type variable during the simulation.

  1. Click Restart button
  2. From the Scope window, select scope axi_vip_0__exdes_adv_mst_active_pt_mem__slv_passive.

  3. Maximize the Objects window. As the simulation is yet to start, observe the Queue and Class dynamic type in the Data Type column. The Value for Queue appears empty while for class it appears null.

  4. On Scope window, double-click axi_vip_0__exdes_adv_mst_active_pt_mem__slv_passive to see the text file.

  5. On the text editor window, click the circle on line number 95 to add a break point.

  6. Click Run All button, the simulation will stop at line number 95. On the Object window master_monitor_transaction_queue value appears empty.