Setting Cell Properties - 2022.1 English

Vivado Design Suite Tutorial: Using Constraints (UG945)

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2022.1 English

Because it can be too time consuming and costly to go back to the RTL after synthesis, you can make changes in the netlist as follows.

  1. Select Edit > Find to open the Find dialog box, as shown in the following figure.
    1. Select Cells from the Find drop-down list.
    2. Under Properties, set PRIMITIVE_TYPE to BMEM.BRAM.
    3. Make sure that Search Hierarchy is selected, as shown in the following figure.
    4. Click OK.

      The Find Results window opens.

  2. Select the Show Search button on the toolbar menu of the Find Results window.
  3. Search for ingressLoop, and select the following cell: fftEngine/fftInst/ingressLoop[7].ingressFifo/

    In the Properties tab of the Cell Properties window, you can see the DOA_REG and DOB_REG are set to zero, indicating that the output registers are disabled.

  4. Generate a custom timing report from this cell directly from the Tcl Console. The Tcl command to enter is:
    report_timing -from [get_cells fftEngine/fftInst/ingressLoop[7].ingressFifo/
    Tip: You can copy and paste the cell name from the General tab of the Cell Properties window into the Tcl Console.
  5. In the upper-right corner of the Tcl Console, click the Maximize button to maximize the window and better view the timing report.
  6. In the data path section of the report, 1.800 ns is added by this RAMB.

  7. Restore the Tcl Console to its normal size.
  8. In the Properties tab of the Cell Properties window, select the DOA_REG and DOB_REG properties for this cell and change their values for "0" to "1."

    You can see two set_property commands run in the Tcl Console.

    set_property DOA_REG {1} [get_cells {fftEngine/fftInst/ingressLoop[7].ingressFifo/
    set_property DOB_REG {1} [get_cells {fftEngine/fftInst/ingressLoop[7].ingressFifo
  9. Run the timing report from the selected cell. The Tcl command to enter is:
    report_timing -from [get_cells fftEngine/fftInst/ingressLoop[7].ingressFifo
  10. Notice that the data path delay for the RAM is now 0.622 ns.