Dynamic Function eXchange (DFX) in AMD FPGAs, SoCs, and adaptive SoCs introduces new design requirements compared to traditional solutions. These requirements include unique approaches to source and run management, as both bottom-up synthesis and multi-pass implementation are needed. Before 2021, only non-project Tcl-based and RTL project-based solutions have been available in the AMD Vivado™ tools. The Vivado tools 2021.2 release introduced an IP-centric project-based environment, which includes new capabilities for block designs and other aspects of IP integrator.
This tutorial summarizes the Vivado tool flow, from project creation to partial bitstream creation for AMD Zynq™ UltraScale+™ MPSoC and RFSoC targets using the Block Design Container feature in IP integrator. This fundamental flow can be used to apply to AMD Virtex™ UltraScale™ , AMD Kintex™ UltraScale™ , and AMD UltraScale+™ device targets as well. The next lab covers the equivalent solution for AMD Versal™ device targets.