This design demonstrates the methodology to debug DFX designs in AMD Versal™ devices using JTAG or HSDP. It covers the following debug scenarios:
- Debug Hub and ILA in the Static Region
- Debug Hub and ILA in a reconfigurable module (rp1rm1)
- Debug Hub and VIO in a reconfigurable module (rp1rm2)
- Debug Hub and two ILA in a reconfigurable module (rp1rm3) to demonstrate the automatic stitching of cores (ILA in this case) to the debug hub
- Static-RM interface for the Debug Hub in RM using Inter NoC Interconnect (NoC INI)
- Enabling HSDP in CIPS (specifically for the VCK190)
- Demonstrate using hardware manager to observe the waveforms generated by ILA
This design also showcases the Abstract Shell feature in IP integrator project mode. Design runs for both standard DFX and abstract shells are created to compare the two approaches. It covers the following features:
- Using the DFX Wizard to create both types of Design Runs.
- Compiling parent runs followed by parallel compilation of child runs.
- Examining the resulting runs to compare the two approaches.
Both solutions will generate a full collection of design checkpoints and partial PDI needed, but the latter will produce results more quickly.