Open individual runs to examine the design results.
- Open either impl_std or impl_abs to examine the parent configuration. This
design image has the full static design along with the contents of rp1rm1 in the RP
- Open the routed design checkpoint for impl_std_child_2. This
has the full static design from the parent run plus the two-counter reconfigurable
module. The static logic is locked so it is shown in orange.
- Open the routed design checkpoint for impl_abs_child_2. This is
the same reconfigurable module as child_2 seen in the previous step, but this time
the orange locked static logic is reduced to a minimal set of logic and routing
around the reconfigurable partition Pblock.
- Finally, source the visualization script to see the expanded routing region that
surrounds this Pblock.
cd ./dfx_debug_abs/dfx_debug_abs.runs/impl_std/hd_visual source pblock_rp1_Routing_AllTiles.tcl
Compare this to the prior image which shows that the user-defined reconfigurable Pblock aligns to a single clock region. This highlighting shows the Pblock range expands left and right into neighboring clock regions to obtain routing resources to improve routability. It does not extend into clock regions above or below, as that would require adding two more complete clock regions to the partial bitstream, more than tripling its size.