The final step before processing through synthesis and implementation is to create an HDL wrapper for the top-level block design, then generate targets for synthesis.
Follow the instructions below or source run_impl.tcl to automate the steps from here through the end of Section 1.
- In the Sources window, right-click on design_1.bd and select Create HDL Wrapper. Keep the Let Vivado
Manage option selected and click OK.
In the sources, design_1_wrapper.v has been created and added to the project. This HDL file instantiates the design_1 block design.
- In the Flow Navigator, click the Generate Block
Design command under the IP INTEGRATOR header. In the resulting
dialog box, keep the Out of context per IP option selected, then click Generate.
This action creates synthesizable output products for each IP in design_1, building out-of-context synthesis runs for each IP. Under the Design Runs tab, you will see the list of synthesis runs for all the IP contained in design_1 (within the static_region hierarchy, so everything not included in the rp1 block container) have been created and are now running. The IP within the block container, for sources rp1rm1 and rp1rm2, have been created but are not running – this action will be requested later.Note: If the design has not been converted to a DFX design, this step will perform that conversion automatically. The definition of a block design container as a DFX partition enforces the need to be in DFX project mode, but nothing to this point has required it.