Verifying the Configurations
- Run the pr_verify command from the Tcl
pr_verify Implement/Config_shift_right_count_up_implement/top_route_design.dcp Implement/Config_shift_left_count_down_import/top_route_design.dcpIf successful, this command returns the following message.
INFO: [Vivado 12-3253] PR_VERIFY: check points Implement/Config_shift_right_count_up/top_route_design.dcp and Implement/Config_shift_left_count_down/top_route_design.dcp are compatible
By default, only the first mismatch (if any) is reported. To see all mismatches, use the
- Close the
Now that the configurations have been verified, you can generate bitstreams and use them to target your selected demonstration board.
count_up. The second configuration implements
- Read the first configuration into
- Generate full and partial bitstreams for this design. Be sure to keep the
bit files in a unique directory related to the full design checkpoint from which
they were created.
Notice that five (or three, if you are using an AMD UltraScale+™ device) bitstreams have been created:
write_bitstream -force -file Bitstreams/Config_RightUp.bit close_project
Config_RightUp.bitThis is the power-up, full design bitstream. The four shift LEDs on the right will shift right and the four count LEDs on the left will count up.
Config_RightUp_pblock_inst_shift_partial.bitThis is the partial bit file for the shift_right module that causes the shift LEDs to shift right.
Config_RightUp_pblock_inst_count_partial.bitThis is the partial bit file for the count_up module that causes the count LEDs to count up.
Config_RightUp_pblock_inst_shift_partial_clear.bitThis is the clearing bit file for the shift_right module for UltraScale devices only. It safely clears a right shift to allow the shift module to be reconfigured.
Config_RightUp_pblock_inst_count_partial_clear.bitThis is the clearing bit file for the count_up module for UltraScale devices only. It safely clears an up count to allow the count module to be reconfigured.
write_bitstream, the names of the bit files currently do not reflect the name of the Reconfigurable Module variant to clarify which image is loaded. The current solution uses the base name given by the
- fileoption and appends the Pblock name of the reconfigurable cell. It is critical to provide enough description in the base name to be able to identify the reconfigurable bit files clearly. All partial bit files have the
_partialpostfix, and all clearing bit files have the
run_dfx.tclto process the entire design through bitstream generation, uses a different technique for generating the bitstreams. Opening a routed design checkpoint issues multiple calls to
write_bitstream, which gives you more control over naming bitstreams and allows for different options (such a bitstream compression) to be applied to full versus partial bitstreams. For example, the names configured in the
Config_shift_right_count_up_implement_full.bitThis is the power-up, full design bitstream.
pblock_shift_shift_right_partial.bitThis is the partial bit file for the
pblock_count_count_up_partial.bitThis is the partial bit file for the
pblock_shift_shift_right_partial_clear.bitThis is the clearing bit file for the
shift_rightmodule for UltraScale devices only.
pblock_count_count_up_partial_clear.bitThis is the clearing bit file for the
count_upmodule for UltraScale devices only.
- Generate full and partial bitstreams for the second configuration, again keeping
the resulting bit files in the appropriate
Similarly, five (or three) bitstreams are created, this time with a different base name.
open_checkpoint Implement/Config_shift_left_count_down_import/top_route_design.dcp write_bitstream -force -file Bitstreams/Config_LeftDown.bit close_project
- Generate a full bitstream with grey boxes, plus blanking bitstreams for the
Reconfigurable Modules. Blanking bitstreams can be used to “erase” an existing
configuration to reduce power consumption. Note: Note: Grey box blanking bitstreams are not the same as clearing bitstreams. Clearing bitstreams are required to prepare the global signal mask for the next partial bitstream, ensuring the GSR event occurs properly.
The base configuration bitstream has no logic for either reconfigurable partition. The
open_checkpoint Checkpoint/static_route_design.dcp update_design -cell inst_count -buffer_ports update_design -cell inst_shift -buffer_ports place_design route_design write_checkpoint -force Checkpoint/config_grey_box.dcp write_bitstream -force -file Bitstreams/config_grey_box.bit close_project
update_designcommands here insert constant drivers (ground) for all outputs of the Reconfigurable Partitions, so these outputs do not float. The term grey box indicates that the modules are not completely empty with these LUTs inserted, as opposed to black boxes, which would have dangling nets in and out of this region. The
route_designcommands ensure they are completely implemented. As valid Reconfigurable Modules, note that these instances also have clearing bitstreams for UltraScale devices only.