The System Edition of the Vivado® Design Suite includes the Vitis™ HLS feature, which has the ability to transform C/C++ design sources into RTL. System Generator has a Vitis HLS block in the Xilinx Blockset/Control Logic and Xilinx Blockset/Index libraries that enables you to bring in C/C++ source files into a System Generator model.
Objectives
After completing this lab, you will be able to incorporate a design, synthesized from C, C++ or SystemC using Vitis HLS, as a block into your MATLAB design.
Procedure
In this step you will first synthesize a C file using Vitis HLS. You will operate within a Vivado DSP design project, using a design file from MATLAB along with an associated HDL wrapper and constraint file. In Part 2, you incorporate the output from Vitis HLS into MATLAB and use the rich simulation features of MATLAB to verify that the C algorithm correctly filters an image.