System Generator for DSP is a design tool in the Vivado® Design Suite that enables you to use the MathWorks® model-based Simulink® design environment for FPGA design. Previous experience with Xilinx® FPGA devices or RTL design methodologies is not required when using System Generator. Designs are captured in the Simulink modeling environment using a Xilinx-specific block set. Downstream FPGA steps including RTL synthesis and implementation (where the gate level design is placed and routed in the FPGA) are automatically performed to produce an FPGA programming bitstream.
Around 100 building blocks are included in the Xilinx-specific DSP block set for Simulink. These blocks include common building blocks such as adders, multipliers and registers. Also included are complex DSP building blocks such as forward-error-correction blocks, FFTs, filters, and memories. These complex blocks leverage Xilinx LogiCORE™ IP to produce optimized results for the selected target device.
In this tutorial, you will do the following.
- Lab 1
- Understand how to create and validate a model using System Generator.
- Make use of workspace variables to easily parameterize your models.
- Synthesize the model into FPGA hardware, and then create a more optimal hardware version of the design.
- Learn how fixed-point data types can be used to trade off accuracy against hardware area and performance.
- Lab 2: Learn Modeling Control System with M-Code, incorporating existing RTL designs, written in Verilog or VHDL, into your design, and import C/C++ source files into a System Generator model by leveraging the tool integration with HLS.
- Lab 3: Learn how to do Timing and Resource Analysis and how to overcome timing violations.
- Lab 4: Learn how to create an efficient design using multiple clock domains.
- Lab 5: Use AXI interfaces and Vivado IP integrator to easily include your model into a larger design.