Asynchronous - 2023.2 English - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-10-18
Version
2023.2 English

Clock relationships are asynchronous when the clocks do not have a fixed phase relationship. This is the case when one of the following is true for the clocks:

  • Do not share any common circuitry in the design and do not have a common primary clock.
  • Do not have a common period within 1000 cycles (unexpandable) and the timing engine cannot properly time them together.
  • Have a common clock but do not share a common node.
  • Are part of a topology that does not ensure a known phase relationship through the clocks auto-derivation process.

If two clocks are synchronous but their common period is very small, the setup paths requirement is too tight for timing to be met. AMD recommends that you treat the two clocks as asynchronous and implement safe asynchronous CDC circuitry.