The Vivado IP integrator provides different ways to set up your design for debugging. You can use one of the following flows to add debug cores to your IP integrator design. The flow you choose depends on your preference and the types of nets and signals that you want to debug.
- Debug interfaces, nets, or both in the block design using the
System ILA core
Use this flow to:
- Perform hardware-software co-verification using the cross-trigger feature of a MicroBlaze™ device, AMD Zynq™ 7000 SoC, or Zynq UltraScale+ MPSoC.
- Verify the interface-level connectivity.
- Netlist insertion flow
Use this flow to analyze I/O ports and internal nets in the post-synthesized design.
For more information on using System ILA in your IP integrator design, see the Vivado Design Suite User Guide: Designing IP Subsystems Using IP Integrator (UG994).