Defining Timing Constraints in Four Steps - 2023.2 English - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

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2023.2 English

The process of defining good constraints is broken into the four major steps shown in the following figure. The steps follow the timing constraints precedence and dependency rules, as well as the logical way of providing information to the timing engine to perform the analysis.

Figure 1. Steps for Developing Timing Constraints

  • The first two steps refer to the timing assertions where the default timing path requirements are derived from the clock waveforms and I/O delay constraints.
  • During the third step, relationships between the asynchronous/exclusive clock domains that share at least one logical path are reviewed. Based on the nature of the relationships, clock groups or false path constraints are entered to ignore the timing analysis on these paths.
  • The last step corresponds to the timing exceptions, where the designer can decide to alter the default timing path requirements by ignoring, relaxing or tightening them with specific constraints.

Constraints creation is associated with constraints identification and constraints validation tasks that are only possible with the various reports generated by the timing engine. The timing engine only works with a fully mapped netlist, for example, after synthesis. While it is possible to enter constraints with an elaborated netlist, it is recommended to create the first set of constraints with the post-synthesis netlist so that analysis and reports on the constraints can be performed interactively.

When creating timing constraints for a new design or completing existing constraints, AMD recommends using the Timing Constraints Wizard to quickly identify missing constraints for the first three steps in the previous figure. The Timing Constraints Wizard follows the methodology described in this section to ensure the design constraints are safe and reliable for proper timing closure. You can find more information on the Timing Constraints Wizard in Vivado Design Suite User Guide: Using Constraints (UG903).

The following sections describe in detail the four steps described above:

Refer to each section for a detailed methodology and use case when you are at the appropriate step in the constraint creation process.