High Fanout Clocks - 2023.2 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-11-29
Version
2023.2 English

A high fanout clock spans almost an entire SLR of an SSI technology device or almost all clock regions of a monolithic device. The following figure shows a high fanout clock that spans almost an entire SLR with the BUFGCE driver shown in red.

Figure 1. High Fanout Clock Spanning an SLR

Note: Using more than 24 clocks in a design might cause issues that require special design considerations or other up-front planning.
Important: In ZHOLD and BUF_IN compensation modes, the MMCM feedback clock path matches the CLKOUT0 clock path in terms of routing track, clock root location, and distribution tracks. Therefore, the feedback clock can be considered a high fanout clock when the clock buffer and clock root are far apart.