When optimizing the code to eliminate reset, commenting out the conditions within the reset
declaration does not create the desired structures and instead creates issues. For
example, the following figure shows three pipeline stages with asynchronous reset used
for each. If you attempt to eliminate the reset condition for two of the pipeline stages
by commenting out the code with the reset condition, the asynchronous reset becomes
enabled (inverted logic of
The optimal way to remove the resets is to create separate sequential logic procedures with one for reset conditions and the other for non-reset conditions, as shown in the following figure.