Pipelining Considerations for Crossing SLRs - 2023.2 English - 2023.1 English

UltraFast Design Methodology Guide for FPGAs and SoCs (UG949)

Document ID
UG949
Release Date
2023-10-18
Version
2023.2 English

The pipeline considerations for crossing SLRs in Virtex UltraScale+ HBM devices are the same as for other UltraScale and Virtex UltraScale+ SSI technology devices.

Paths from fabric logic in SLR2 to the HBM AXI Interfaces in SLR0 often require five or more pipeline stages to meet timing. Thoughtful design planning of Virtex UltraScale+ HBM devices can reduce the need for additional pipeline stages and reduce routing congestion. The following figure shows an example of SLR crossings to the HBM AXI Interfaces from SLR2.

Tip: Use auto-pipelining (e.g., AXI Register Slice IP) to ensure timing closure between the HBM interfaces and any SLR at 450 MHz.
Figure 1. HBM Sub-Optimal Design Planning (left) versus Optimal Design Planning (right)