To take advantage of the existing DSP primitive features, the following example shows a multiplier with synchronous reset.
In this circuit, the DSP48 primitive is inferred with all pipeline registers packed within the DSP primitive (AREG/BREG=1, MREG=1, PREG=1).
The following figure shows the coding example for multiplier pipeline registers that use a synchronous reset.
This coding example has the following advantages:
- Optimal resource usage
- Better performance and lower power
- Lower number of endpoints