To use control set mapping you can apply attributes to the nets connected to enable/reset signals, which will force synthesis to use the CE/R pin.
In the following figure, the enable signal (
en) is only connected to one
flip-flop. Therefore, the synthesis engine connected the en signal to the FDRE/D pin
cone of logic. Note that the CE pin is tied to logic 1.
To override this default behavior, you can use the DIRECT_ENABLE attribute. For example, the
following figure shows how to connect the enable signal (
en) to the CE
pin of the register by adding the DIRECT_ENABLE attribute to the port/signal.
The following figure shows RTL code in which either
int_rst can reset the register. By default, both are mapped to the reset pin cone of logic.
You can use the DIRECT_RESET attribute to specify which reset signal to connect to the register reset pin. For example, the following figure shows how to use the DIRECT_RESET attribute to connect only the
global_rst signal to the register FDRE/R pin and connect the
int_rst signal to the FDRE/D cone of logic.