ADDMACC_MACRO - 2023.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-05-17
Version
2023.1 English

Macro: Adder/Multiplier/Accumulator

Introduction

ADDMACC_MACRO simplifies the instantiation of the DSP48 block when used as a pre-add, multiply accumulate function. It features parameterizable input and output widths and latency that ease the integration of DSP48 block into HDL.

Port Descriptions

Port Direction Width Function
PRODUCT Output Variable width, equals the value of the WIDTH_A attribute plus the value of the WIDTH_B attribute. Primary data output.
PREADD1 Input Variable, see WIDTH_PREADD attribute. Preadder data input.
PREADD2 Input Variable, see WIDTH_PREADD attribute. Preadder data input
MULTIPLIER Input Variable, see WIDTH_MULTIPLIER attribute. Multiplier data input
CARRYIN Input 1 Carry input
CLK Input 1 Clock
CE Input 1 Clock enable
LOAD Input 1 Load
LOAD_DATA Input Variable, see WIDTH_PRODUCT attribute. In a DSP slice, when LOAD is asserted, loads P with A*B+LOAD_DATA.
RST Input 1 Synchronous Reset

Design Entry Method

This unimacro is a parameterizable version of the primitive, and can be instantiated only.
Instantiation Yes
Inference No
IP Catalog No
Macro support Recommended

Available Attributes

Attribute Type Allowed Values Default Description
WIDTH_PREADD INTEGER 1 to 24 24 Controls the width of PREADD1 and PREADD2 inputs.
WIDTH_MULTIPLIER INTEGER 1 to 18 18 Controls the width of MULTIPLIER input.
WIDTH_PRODUCT INTEGER 1 to 48 48 Controls the width of MULTIPLIER output.
LATENCY INTEGER 0, 1, 2, 3, 4 3 Number of pipeline registers
  • 1: MREG == 1
  • 2: AREG == BREG == 1 and MREG == 1 or MREG == 1 and PREG == 1
  • 3: AREG == BREG == 1 and MREG == 1 and PREG == 1
  • 4: AREG == BREG == 2 and MREG == 1 and PREG == 1
DEVICE STRING "7SERIES" "7SERIES" Target hardware architecture.

VHDL Instantiation Template

Unless they already exist, copy the following four statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;

-- ADDMACC_MACRO: Add and Multiple Accumulate Function implemented in a DSP48E
--                7 Series
-- Xilinx HDL Language Template, version 2023.1

ADDMACC_MACRO_inst : ADDMACC_MACRO
generic map (
   DEVICE => "7SERIES",  -- Target Device: "7SERIES", "VIRTEX6", "SPARTAN6"
   LATENCY => 4,         -- Desired clock cycle latency, 1-4
   WIDTH_PREADD => 25,   -- Pre-Adder input bus width, 1-25
   WIDTH_MULTIPLIER => 18, -- Multiplier input bus width, 1-18
   WIDTH_PRODUCT => 48)    -- MACC output width, 1-48
port map (
   PRODUCT => PRODUCT,     -- MACC result output, width defined by WIDTH_PRODUCT generic
   MULTIPLIER => MULTIPLIER, -- Multiplier data input, width determined by WIDTH_MULTIPLIER generic
   PREADDER1 => PREADDER1,   -- Preadder data input, width determined by WIDTH_PREADDER generic
   PREADDER2 => PREADDER2,   -- Preadder data input, width determined by WIDTH_PREADDER generic
   CARRYIN => CARRYIN, -- 1-bit carry-in input
   CE => CE,      -- 1-bit input clock enable
   CLK => CLK,    -- 1-bit clock input
   LOAD => LOAD, -- 1-bit accumulator load input
   LOAD_DATA => LOAD_DATA, -- Accumulator load data input, width defined by WIDTH_PRODUCT generic
   RST => RST    -- 1-bit input active high synchronous reset
);
-- End of ADDMACC_MACRO_inst instantiation

Verilog Instantiation Template


// ADDMACC_MACRO: Variable width & latency - Pre-Add -> Multiplier -> Accumulate
//                function implemented in a DSP48E
//                7 Series
// Xilinx HDL Language Template, version 2023.1

ADDMACC_MACRO #(
   .DEVICE("7SERIES"),    // Target Device: "7SERIES"
   .LATENCY(4),           // Desired clock cycle latency, 0-4
   .WIDTH_PREADD(25),     // Pre-adder input width, 1-25
   .WIDTH_MULTIPLIER(18), // Multiplier input width, 1-18
   .WIDTH_PRODUCT(48)     // MACC output width, 1-48
) ADDMACC_MACRO_inst (
   .PRODUCT(PRODUCT),   // MACC result output, width defined by WIDTH_PRODUCT parameter
   .CARRYIN(CARRYIN),   // 1-bit carry-in input
   .CLK(CLK),           // 1-bit clock input
   .CE(CE),             // 1-bit clock enable input
   .LOAD(LOAD),         // 1-bit accumulator load input
   .LOAD_DATA(LOAD_DATA),   // Accumulator load data input, width defined by WIDTH_PRODUCT parameter
   .MULTIPLIER(MULTIPLIER), // Multiplier data input, width defined by WIDTH_MULTIPLIER parameter
   .PREADD2(PREADD2),   // Preadder data input, width defined by WIDTH_PREADD parameter
   .PREADD1(PREADD1),   // Preadder data input, width defined by WIDTH_PREADD parameter
   .RST(RST)            // 1-bit active high synchronous reset
);

// End of ADDMACC_MACRO_inst instantiation