BUFGCE_1 - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: Global Clock Buffer with Clock Enable and Output State 1

Introduction

This design element is a global clock buffer with a single gated input. Its O output is "1" when clock enable (CE) is Low (inactive). When clock enable (CE) is High, the I input is transferred to the O output.

Logic Table

Inputs Outputs
I CE O
X 0 1
I 1 I

Port Descriptions

Port Direction Width Function
CE Input 1 Clock buffer active-High enable.
I Input 1 Clock input.
O Output 1 Clock output.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
--           7 Series
-- Xilinx HDL Language Template, version 2023.2

BUFGCE_1_inst : BUFGCE_1
port map (
   O => O,   -- 1-bit output: Clock output
   CE => CE, -- 1-bit input: Clock enable input for I0
   I => I    -- 1-bit input: Primary clock
);

-- End of BUFGCE_1_inst instantiation

Verilog Instantiation Template


// BUFGCE_1: Global Clock Buffer with Clock Enable and Output State 1
//           7 Series
// Xilinx HDL Language Template, version 2023.2

BUFGCE_1 BUFGCE_1_inst (
   .O(O),   // 1-bit output: Clock output
   .CE(CE), // 1-bit input: Clock enable input for I0
   .I(I)    // 1-bit input: Primary clock
);

// End of BUFGCE_1_inst instantiation

Related Information

  • 7 Series FPGAs Clocking Resources User Guide (UG472)