COUNTER_TC_MACRO - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Macro: Counter with Terminal Count

Introduction

COUNTER_TC_MACRO simplifies the instantiation of the DSP48 block when used as a terminal count, up/down counter. It features parameterizable output width, terminal count values, count by and count direction to ease the integration of DSP48 block into HDL.

Port Descriptions

Port Direction Width Function
TC Output 1 Terminal count goes high when TC_VALUE is reached
Q Output Variable, see WIDTH_DATA attribute. Counter output
CE Input 1 Clock Enable
CLK Input 1 Clock
RST Input 1 Synchronous Reset

Design Entry Method

This unimacro is a parameterizable version of the primitive, and can be instantiated only.
Instantiation Yes
Inference No
IP Catalog No
Macro support Recommended

Available Attributes

Attribute Type Allowed Values Default Description
RESET_UPON_TC BOOLEAN True, False False

Specifies whether to reset the counter upon reaching terminal count

DEVICE STRING "7SERIES" "7SERIES"

Target hardware architecture.

DIRECTION STRING "UP", "DOWN" "UP"

Count up versus count down.

COUNT_BY HEX Any 48-bit value 000000000001

Count by n; takes precedence over WIDTH_DATA.

TC_VALUE HEX Any 48-bit value All zeros

Terminal count value.

WIDTH_DATA INTEGER 1-48 48

Specifies counter width.

VHDL Instantiation Template

Unless they already exist, copy the following four statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;
library UNIMACRO;
use unimacro.Vcomponents.all;

-- COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
--                   7 Series
-- Xilinx HDL Language Template, version 2023.2

COUNTER_TC_MACRO_inst : COUNTER_TC_MACRO
generic map (
   COUNT_BY => X"000000000001", -- Count by value
   DEVICE => "7SERIES",         -- Target Device: "VIRTEX5", "7SERIES"
   DIRECTION => "UP",            -- Counter direction "UP" or "DOWN"
   RESET_UPON_TC => "FALSE",      -- Reset counter upon terminal count, TRUE or FALSE
   TC_VALUE => X"000000000000", -- Terminal count value
   WIDTH_DATA => 48)            -- Counter output bus width, 1-48
port map (
   Q => Q,        -- Counter ouput, width determined by WIDTH_DATA generic
   TC => TC,      -- 1-bit terminal count output, high = terminal count is reached
   CLK => CLK,    -- 1-bit clock input
   CE => CE,      -- 1-bit clock enable input
   RST => RST       -- 1-bit active high synchronous reset
);
-- End of COUNTER_TC_MACRO_inst instantiation

Verilog Instantiation Template


// COUNTER_TC_MACRO: Counter with terminal count implemented in a DSP48E
//                   7 Series
// Xilinx HDL Language Template, version 2023.2

COUNTER_TC_MACRO #(
   .COUNT_BY(48'h000000000001), // Count by value
   .DEVICE("7SERIES"),          // Target Device: "7SERIES"
   .DIRECTION("UP"),            // Counter direction, "UP" or "DOWN"
   .RESET_UPON_TC("FALSE"), // Reset counter upon terminal count, "TRUE" or "FALSE"
   .TC_VALUE(48'h000000000000), // Terminal count value
   .WIDTH_DATA(48)              // Counter output bus width, 1-48
) COUNTER_TC_MACRO_inst (
   .Q(Q),     // Counter output bus, width determined by WIDTH_DATA parameter
   .TC(TC),   // 1-bit terminal count output, high = terminal count is reached
   .CLK(CLK), // 1-bit positive edge clock input
   .CE(CE),   // 1-bit active high clock enable input
   .RST(RST)  // 1-bit active high synchronous reset
);

// End of COUNTER_TC_MACRO_inst instantiation