FRAME_ECCE2 - 2023.2 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-10-18
Version
2023.2 English

Primitive: Configuration Frame Error Correction

Introduction

This design element enables the dedicated, built-in Error Correction Code (ECC) for the configuration memory of the FPGA. This element contains outputs that allow monitoring of the status of the ECC circuitry and the status of the readback CRC circuitry.

Port Descriptions

Port Direction Width Function
CRCERROR Output 1 Output indicating a CRC error.
ECCERROR Output 1 Output indicating an ECC error.
ECCERRORSINGLE Output 1 Output Indicating single-bit Frame ECC error detected.
FAR<25:0> Output 26 Frame Address Register Value output.
SYNBIT<4:0> Output 5 Output bit address of error.
SYNDROME<12:0> Output 13 Output location of erroneous bit.
SYNDROMEVALID Output 1 Frame ECC output indicating the SYNDROME output is valid.
SYNWORD<6:0> Output 7 Word output in the frame where an ECC error has been detected.

Design Entry Method

Instantiation Recommended
Inference No
IP Catalog No
Macro support No

Available Attributes

Attribute Type Allowed Values Default Description
FARSRC STRING "EFAR", "FAR" "EFAR" Sedts whether the output of the FAR[25:0] configuration register points to the FAR or EFAR. Sets configuration option register bit CTL0[7].
FRAME_RBT_IN _FILENAME STRING String representing file name and location “NONE” This file is output by the ICAP_E2 model and it contains Frame Data information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model will parse this file, calculate ECC and output any error conditions.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- FRAME_ECCE2: Configuration Frame Error Correction
--              7 Series
-- Xilinx HDL Language Template, version 2023.2

FRAME_ECCE2_inst : FRAME_ECCE2
generic map (
   FARSRC => "EFAR",                -- Determines if the output of FAR[25:0] configuration register points
                                    -- to the FAR or EFAR. Sets configuration option register bit CTL0[7].
   FRAME_RBT_IN_FILENAME => "NONE"  -- This file is output by the ICAP_E2 model and it contains Frame Data
                                    -- information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
                                    -- will parse this file, calculate ECC and output any error conditions.
)
port map (
   CRCERROR => CRCERROR,             -- 1-bit output: Output indicating a CRC error.
   ECCERROR => ECCERROR,             -- 1-bit output: Output indicating an ECC error.
   ECCERRORSINGLE => ECCERRORSINGLE, -- 1-bit output: Output Indicating single-bit Frame ECC error detected.
   FAR => FAR,                       -- 26-bit output: Frame Address Register Value output.
   SYNBIT => SYNBIT,                 -- 5-bit output: Output bit address of error.
   SYNDROME => SYNDROME,             -- 13-bit output: Output location of erroneous bit.
   SYNDROMEVALID => SYNDROMEVALID,   -- 1-bit output: Frame ECC output indicating the SYNDROME output is
                                     -- valid.

   SYNWORD => SYNWORD                -- 7-bit output: Word output in the frame where an ECC error has been
                                     -- detected.

);

-- End of FRAME_ECCE2_inst instantiation

Verilog Instantiation Template


// FRAME_ECCE2: Configuration Frame Error Correction
//              7 Series
// Xilinx HDL Language Template, version 2023.2

FRAME_ECCE2 #(
   .FARSRC("EFAR"),                // Determines if the output of FAR[25:0] configuration register points to
                                   // the FAR or EFAR. Sets configuration option register bit CTL0[7].
   .FRAME_RBT_IN_FILENAME("NONE")  // This file is output by the ICAP_E2 model and it contains Frame Data
                                   // information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
                                   // will parse this file, calculate ECC and output any error conditions.
)
FRAME_ECCE2_inst (
   .CRCERROR(CRCERROR),             // 1-bit output: Output indicating a CRC error.
   .ECCERROR(ECCERROR),             // 1-bit output: Output indicating an ECC error.
   .ECCERRORSINGLE(ECCERRORSINGLE), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
   .FAR(FAR),                       // 26-bit output: Frame Address Register Value output.
   .SYNBIT(SYNBIT),                 // 5-bit output: Output bit address of error.
   .SYNDROME(SYNDROME),             // 13-bit output: Output location of erroneous bit.
   .SYNDROMEVALID(SYNDROMEVALID),   // 1-bit output: Frame ECC output indicating the SYNDROME output is
                                    // valid.

   .SYNWORD(SYNWORD)                // 7-bit output: Word output in the frame where an ECC error has been
                                    // detected.

);

// End of FRAME_ECCE2_inst instantiation

Related Information

  • 7 Series FPGAs Configuration User Guide (UG470)