This section categorizes, by function, the circuit design elements for 7 series FPGAs and AMD Zynq™ 7000 SoC devices described in detail later in this guide. The elements (primitives and macros) are listed in alphanumeric order under each functional category.
Advanced
| Design Element | Description |
|---|---|
| XADC | Primitive: Dual 12-Bit 1MSPS Analog-to-Digital Converter |
Arithmetic Functions
| Design Element | Description |
|---|---|
| DSP48E1 | Primitive: 48-bit Multi-Functional Arithmetic Block |
Clock Components
| Design Element | Description |
|---|---|
| BUFG | Primitive: Global Clock Simple Buffer |
| BUFGCE | Primitive: Global Clock Buffer with Clock Enable |
| BUFGCE_1 | Primitive: Global Clock Buffer with Clock Enable and Output State 1 |
| BUFGCTRL | Primitive: Global Clock Control Buffer |
| BUFGMUX | Primitive: Global Clock Mux Buffer |
| BUFGMUX_1 | Primitive: Global Clock Mux Buffer with Output State 1 |
| BUFGMUX_CTRL | Primitive: 2-to-1 Global Clock MUX Buffer |
| BUFH | Primitive: HROW Clock Buffer for a Single Clocking Region |
| BUFHCE | Primitive: HROW Clock Buffer for a Single Clocking Region with Clock Enable |
| BUFIO | Primitive: Local Clock Buffer for I/O |
| BUFMR | Primitive: Multi-Region Clock Buffer |
| BUFMRCE | Primitive: Multi-Region Clock Buffer with Clock Enable |
| BUFR | Primitive: Regional Clock Buffer for I/O and Logic Resources within a Clock Region |
| MMCME2_ADV | Primitive: Advanced Mixed Mode Clock Manager |
| MMCME2_BASE | Primitive: Base Mixed Mode Clock Manager |
| PLLE2_ADV | Primitive: Advanced Phase Locked Loop (PLL) |
| PLLE2_BASE | Primitive: Base Phase Locked Loop (PLL) |
Config/BSCAN Components
| Design Element | Description |
|---|---|
| BSCANE2 | Primitive: Boundary-Scan User Instruction |
| CAPTUREE2 | Primitive: Register Capture |
| DNA_PORT | Primitive: Device DNA Access Port |
| EFUSE_USR | Primitive: 32-bit non-volatile design ID |
| FRAME_ECCE2 | Primitive: Configuration Frame Error Correction |
| ICAPE2 | Primitive: Internal Configuration Access Port |
| STARTUPE2 | Primitive: STARTUP Block |
| USR_ACCESSE2 | Primitive: Configuration Data Access |
I/O Components
| Design Element | Description |
|---|---|
| DCIRESET | Primitive: Digitally Controlled Impedance Reset Component |
| IBUF | Primitive: Input Buffer |
| IBUF_IBUFDISABLE | Primitive: Single-ended Input Buffer with Input Disable |
| IBUF_INTERMDISABLE | Primitive: Single-ended Input Buffer with Input Termination Disable and Input Disable |
| IBUFDS | Primitive: Differential Signaling Input Buffer |
| IBUFDS_DIFF_OUT | Primitive: Differential Signaling Input Buffer With Differential Output |
| IBUFDS_DIFF_OUT _IBUFDISABLE | Primitive: Input Differential Buffer with Input Disable and Differential Output |
| IBUFDS_DIFF_OUT _INTERMDISABLE | Primitive: Input Differential Buffer with Input Termination Disable, Input Disable, and Differential Output |
| IBUFDS_IBUFDISABLE | Primitive: Input Differential Buffer with Input Path Disable |
| IBUFDS_INTERMDISABLE | Primitive: Input Differential Buffer with Input Termination Disable and Input Disable |
| IBUFDS_GTE2 | Primitive: Gigabit Transceiver Buffer |
| IDELAYCTRL | Primitive: IDELAYE2/ODELAYE2 Tap Delay Value Control |
| IDELAYE2 | Primitive: Input Fixed or Variable Delay Element |
| IN_FIFO | Primitive: Input First-In, First-Out (FIFO) |
| IOBUF | Primitive: Bi-Directional Buffer |
| IOBUF_DCIEN | Primitive: Bi-Directional Single-ended Buffer with DCI and Input Disable. |
| IOBUF_INTERMDISABLE | Primitive: Bi-Directional Single-ended Buffer with Input Termination Disable and Input Path Disable |
| IOBUFDS | Primitive: 3-State Differential Signaling I/O Buffer with Active-Low Output Enable |
| IOBUFDS_DCIEN | Primitive: Bi-Directional Differential Buffer with DCI Enable/Disable and Input Disable |
| IOBUFDS_DIFF_OUT | Primitive: Differential Bi-directional Buffer with Differential Output |
| IOBUFDS_DIFF_OUT_DCIEN | Primitive: Bi-Directional Differential Buffer with DCI Disable, Input Disable, and Differential Output |
| IOBUFDS_DIFF_OUT _INTERMDISABLE | Primitive: Bi-Directional Differential Buffer with Input Termination Disable, Input Disable, and Differential Output |
| IOBUFDS_INTERMDISABLE | Primitive: Bi-Directional Differential Buffer with Input Termination Disable and Input Disable |
| ISERDESE2 | Primitive: Input SERial/DESerializer with Bitslip |
| KEEPER | Primitive: KEEPER Symbol |
| OBUF | Primitive: Output Buffer |
| OBUFDS | Primitive: Differential Signaling Output Buffer |
| OBUFT | Primitive: 3-State Output Buffer with Active-Low Output Enable |
| OBUFTDS | Primitive: 3-State Output Buffer with Differential Signaling, Active-Low Output Enable |
| ODELAYE2 | Primitive: Output Fixed or Variable Delay Element |
| OSERDESE2 | Primitive: Output SERial/DESerializer with bitslip |
| OUT_FIFO | Primitive: Output First-In, First-Out (FIFO) Buffer |
| PULLDOWN | Primitive: Resistor to GND for Input Pads, Open-Drain, and 3-State Outputs |
| PULLUP | Primitive: Resistor to VCC for Input PADs, Open-Drain, and 3-State Outputs |
RAM/ROM
| Design Element | Description |
|---|---|
| FIFO18E1 | Primitive: 18Kb FIFO (First-In-First-Out) Block RAM Memory |
| FIFO36E1 | Primitive: 36Kb FIFO (First-In-First-Out) Block RAM Memory |
| RAM128X1D | Primitive: 128-Deep by 1-Wide Dual Port Random Access Memory (Select RAM) |
| RAM128X1S | Primitive: 128-Deep by 1-Wide Random Access Memory (Select RAM) |
| RAM256X1S | Primitive: 256-Deep by 1-Wide Random Access Memory (Select RAM) |
| RAM32M | Primitive: 32-Deep by 8-bit Wide Multi Port Random Access Memory (Select RAM) |
| RAM32X1D | Primitive: 32-Deep by 1-Wide Static Dual Port Synchronous RAM |
| RAM32X1S | Primitive: 32-Deep by 1-Wide Static Synchronous RAM |
| RAM32X1S_1 | Primitive: 32-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock |
| RAM32X2S | Primitive: 32-Deep by 2-Wide Static Synchronous RAM |
| RAM64M | Primitive: 64-Deep by 4-bit Wide Multi Port Random Access Memory (Select RAM) |
| RAM64X1D | Primitive: 64-Deep by 1-Wide Dual Port Static Synchronous RAM |
| RAM64X1S | Primitive: 64-Deep by 1-Wide Static Synchronous RAM |
| RAM64X1S_1 | Primitive: 64-Deep by 1-Wide Static Synchronous RAM with Negative-Edge Clock |
| RAMB18E1 | Primitive: 18K-bit Configurable Synchronous Block RAM |
| RAMB36E1 | Primitive: 36K-bit Configurable Synchronous Block RAM |
| ROM128X1 | Primitive: 128-Deep by 1-Wide ROM |
| ROM256X1 | Primitive: 256-Deep by 1-Wide ROM |
| ROM32X1 | Primitive: 32-Deep by 1-Wide ROM |
| ROM64X1 | Primitive: 64-Deep by 1-Wide ROM |
Registers/Latches
| Design Element | Description |
|---|---|
| FDCE | Primitive: D Flip-Flop with Clock Enable and Asynchronous Clear |
| FDPE | Primitive: D Flip-Flop with Clock Enable and Asynchronous Preset |
| FDRE | Primitive: D Flip-Flop with Clock Enable and Synchronous Reset |
| FDSE | Primitive: D Flip-Flop with Clock Enable and Synchronous Set |
| IDDR | Primitive: Input Double Data-Rate Register |
| IDDR_2CLK | Primitive: Input Double Data-Rate Register with Dual Clock Inputs |
| LDCE | Primitive: Transparent Data Latch with Asynchronous Clear and Gate Enable |
| LDPE | Primitive: Transparent Data Latch with Asynchronous Preset and Gate Enable |
| ODDR | Primitive: Dedicated Double Data Rate (DDR) Output Register |
Slice/CLB Primitives
| Design Element | Description |
|---|---|
| CARRY4 | Primitive: Fast Carry Logic with Look Ahead |
| CFGLUT5 | Primitive: 5-input Dynamically Reconfigurable Look-Up Table (LUT) |
| LUT1 | Primitive: 1-Bit Look-Up Table with General Output |
| LUT2 | Primitive: 2-Bit Look-Up Table with General Output |
| LUT3 | Primitive: 3-Bit Look-Up Table with General Output |
| LUT4 | Primitive: 4-Bit Look-Up-Table with General Output |
| LUT5 | Primitive: 5-Input Lookup Table with General Output |
| LUT6 | Primitive: 6-Input Lookup Table with General Output |
| LUT6_2 | Primitive: Six-input, 2-output, Look-Up Table |
| MUXF7 | Primitive: 2-to-1 Look-Up Table Multiplexer with General Output |
| MUXF8 | Primitive: 2-to-1 Look-Up Table Multiplexer with General Output |
| SRL16E | Primitive: 16-Bit Shift Register Look-Up Table (LUT) with Clock Enable |
| SRLC32E | Primitive: 32 Clock Cycle, Variable Length Shift Register Look-Up Table (LUT) with Clock Enable |