IBUF - 2023.1 English

Vivado Design Suite 7 Series FPGA and Zynq 7000 SoC Libraries Guide (UG953)

Document ID
UG953
Release Date
2023-05-17
Version
2023.1 English

Primitive: Input Buffer

Introduction

This design element is automatically inserted (inferred) by the synthesis tool to any signal directly connected to a top-level input or in-out port of the design. You should generally let the synthesis tool infer this buffer. However, it can be instantiated into the design if required. In order to do so, connect the input port (I) directly to the associated top-level input or in-out port, and connect the output port (O) to the logic sourced by that port. Modify any necessary generic maps (VHDL) or named parameter value assignment (Verilog) to change the default behavior of the component.

Port Descriptions

Port Direction Width Function
O Output 1 Buffer output.
I Input 1 Buffer input.

Design Entry Method

Instantiation Yes
Inference Recommended
IP Catalog No
Macro support No

In general, IBUFs are inferred by the synthesis tool for specified top-level input ports to the design, so it is not necessary to specify them in the source code. However, if desired, they can be manually instantiated by copying the instantiation code from the appropriate Libraries Guide HDL template and pasting it into the top-level entity/module of your code. You should always put all I/O components on the top-level of the design to help facilitate hierarchical design methods. Connect the I port directly to the top-level input port of the design and the O port to the logic in which this input is to source. Specify the desired generic/defparam values to configure the proper behavior of the buffer.

Available Attributes

Attribute Type Allowed Values Default Description
IBUF_LOW_PWR BOOLEAN TRUE, FALSE TRUE When set to TRUE, allows for reduced power when using differential or referenced (requiring VREF) input standards like LVDS or HSTL. A setting of FALSE demands more power but delivers higher performance characteristics.Consult the7 Series FPGA SelectIO Resources User Guide (UG471) for details.
IOSTANDARD STRING See Data Sheet "DEFAULT" Assigns an I/O standard to the element.

VHDL Instantiation Template

Unless they already exist, copy the following two statements and paste them before the entity declaration.
Library UNISIM;
use UNISIM.vcomponents.all;

-- IBUF: Single-ended Input Buffer
--       7 Series
-- Xilinx HDL Language Template, version 2023.1

IBUF_inst : IBUF
generic map (
   IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   IOSTANDARD => "DEFAULT")
port map (
   O => O,     -- Buffer output
   I => I      -- Buffer input (connect directly to top-level port)
);

-- End of IBUF_inst instantiation

Verilog Instantiation Template


// IBUF: Single-ended Input Buffer
//       7 Series
// Xilinx HDL Language Template, version 2023.1

IBUF #(
   .IBUF_LOW_PWR("TRUE"),  // Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
   .IOSTANDARD("DEFAULT")  // Specify the input I/O standard
) IBUF_inst (
   .O(O),     // Buffer output
   .I(I)      // Buffer input (connect directly to top-level port)
);

// End of IBUF_inst instantiation

Related Information

  • 7 Series FPGAs SelectIO Resources User Guide (UG471)